Its cost is estimated to be in the hundreds of thousands--perhaps even over a million bucks.
During the conference, IBM said that the processor is based on CISC architecture and contains 1.4 billion transistors on a 512 sq. mm chip fabricated on 45-nm PD SOI technology
. The chip provides 64KB L1 instruction cache, 128KB L1 data cache, and 1.5MB private L2 cache per core. It also uses a pair of co-processors for cryptographic operations.
Additionally, a 4-node system uses 19.5MB of SRAM for L1 private cache, 144MB for L2 private cache, 576MB of eDRAM for L3 cache, and 768MB of eDRAM for a level-4 cache.
IBM engineer Brian Curran said Tuesday that the z196 uses 1079 different instructions. 75 of these instructions can be used by millicode (IBM's term for instructions internally executed by the processor) only, and 219 can be executed by millicode. An additional 24 instructions are "conditionally executed" by millicode.
Curran said that the z196 processor will be available sometime in September.
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